1. Field of the Invention
The present invention relates generally to field-effect transistors (FET). More particularly, the present invention relates to an apparatus and method for forming a vertical double-gated FET having a pad nitride layer with a plurality of etch stop layers periodically there-through which provide the ability to fabricate a plurality of vertical-channel FETs with a variety of gate lengths on the same die.
2. Description of Related Art
Over the years, it has been indispensably necessary to reduce semiconductor device size in order to increase performance and decrease power consumption. As a result of such smaller semiconductors, an increased number of smaller integrated circuit contacts are required for making connections to such semiconductors.
In keeping up with modern technology, integrated circuits, such as field effect transistors (FETs), may be formed with gate lengths scaled below 50 nm. However, as gate lengths are formed below 50 nm, FET scaling becomes limited by the formation and control of such gates. Furthermore, the smaller FETs may require a larger number of contacts on a single chip. The limitations of controlling gates scaled below 50 nm, as well as the requirement of a plurality of contacts on a single FET, produce a variety of problems such as alignment problems, problems associated with making connections with contacts, gate length control, and low FET resistance, for example. Overall, the above problems have the effect of decreasing semiconductor reliability and performance, as well as leading to increased production costs.
Attempts have been made to both improve the reliability and performance of smaller semiconductors and increase the surface space on the substrate to provide an increased number of connection contacts connected to the substrate. Techniques provided to overcome the above problems have included, for example, merely defining the gate lithographically with high step heights, controlling and forming the gate by forming wrap-around gates with vertical carrier transport, and selective epitaxial growth procedures to form an xe2x80x9cair-bridgexe2x80x9d silicon structure.
However, the known techniques of forming FETs having vertical gates and increased surface space are not sufficient in forming and controlling smaller gate electrodes, such as those scaled below 50 nm, as well as increased surface space as a result of such smaller gates. Forming and controlling smaller gates by known techniques leads to semiconductors having decreased performance and reliability. Therefore, as integrated circuits become smaller, and therewith the gate electrodes, further improvements are needed in forming and controlling smaller gate dimensions. Improvements are also needed in providing semiconductors having the ability to accommodate and connect with a plurality of contacts having varying channel dimensions, such as varying lengths. In general, semiconductor circuits rely on transistors with different current drives, such as integrated circuits requiring channels with different device widths and lengths. While varying device widths are achievable with vertical transistors, there is a need for methods to form transistors of varying device lengths.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide an improved structure and method of making a vertical double-gated FET adapted to accommodate a plurality of gate lengths on the same die.
Another object of the present invention is to provide an improved structure and method of forming gates scaled below 50 nm.
It is yet another object of the present invention to provide an improved structure and method of making a FET adapted to contact with a plurality of contacts having varying gate lengths.
Yet another object of the present invention is to provide an improved structure and method of making a plurality of vertical-channel FETs with a variety of gate lengths on the same die.
Yet another object of the present invention is to provide an improved structure and method of making a FET with increased performance and reliability.
Yet another object of this invention is to form transistors with varying gate lengths in the vertical dimension.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.
The above and other objects and advantages, which will be apparent to one of skill in the art, are achieved in the present invention which is directed to, in a first aspect, a method of forming a FET, and the FET made, by first providing a substrate, preferably a silicon on insulator, silicon on sapphire, or bulk silicon wafer, with a pad layer thereover. In the preferred embodiment, the pad layer has a plurality of etch stop layers periodically therethrough. The etch stop layers may be provided through the pad layers equidistantly during deposition of the pad layer, or alternatively, the etch stop layers may be deposited at varying depths during deposition of the pad layer.
In the preferred embodiment, a plurality of contacts having varying dimensions are provided for connection to the substrate. In connecting the plurality of contacts to the substrate, a plurality of openings are first formed within the substrate whereby first and second openings traverse through the pad and plurality of etch stop layers, while other openings traverse through the pad layer stopping at a selected one of the plurality of etch stop layers. A vertical channel is then formed in the first opening traversing through the pad and plurality of etch stop layers, wherein first and second gates are then formed within such vertical channel. Subsequently, the plurality of contacts are connected to the substrate whereby at least one of the contacts connects to the vertical channel, at least one of the contacts connects to the second opening traversing through the pad and plurality of etch stop layers, while still other contacts of the plurality of contacts connect to the first and second gates. In the preferred embodiment, the substrate may also be provided with source and drain regions wherein the source and drain regions are provided at the first and second openings traversing through the pad and plurality of etch stop layers. Thus, the present invention provides a first vertical gate FET adapted to be connected to a single die wherein the die has on a surface thereof at least a second vertical gate FET having a differing gate length than a gate length of the first FET, the second FET being made by the above process.
In another embodiment, the present invention is directed to a method of forming a FET, and the FET made, wherein a substrate having an active region is provided, such as a silicon on insulator, silicon on sapphire, or bulk silicon wafer. A pad layer is provided over the substrate whereby the pad layer further has a plurality of etch stop layers. Preferably, the pad layer comprises a first pad layer and a second pad layer. More preferably, the pad layer comprises first a pad oxide layer having over a surface thereof a pad nitride layer. The plurality of etch stop layers preferably comprise a plurality of oxide etch stop layers.
Subsequently, a vertical channel, preferably comprising a grown active layer, is provided in the substrate whereby the vertical channel traverses through the pad and plurality of etch stop layers. Preferably, the vertical channel is formed in the trench by growing an underlying portion of a conductive layer of the substrate. Next, first and second gates are provided within the vertical channel. A plurality of contacts having varying depths are provided. A plurality of openings are then formed within the substrate wherein the openings are adapted to connect with selected ones of the plurality of contacts having varying dimensions. Preferably, a first opening of the plurality of openings traverses through the substrate connecting to the vertical channel, while a second opening traverses through the substrate connecting to the active region, while still other openings traverse through the pad layer stopping at a selected one of the plurality of etch stop layers.
The first and second gates may then be extended by depositing additional gate material over the surface of the openings which stop at selected ones of the plurality of etch stop layers. The plurality of contacts are then connected to the substrate whereby at least a first contact of the plurality of contacts connects to the first opening over the vertical channel, while at least a second contact connects to the second opening over the active region, while still other contacts of the plurality of contacts connect to the first and second extended gates, thereby providing a vertical gate FET having the plurality of contacts with varying depths.
In yet another embodiment, the present invention is directed to a method of forming multi-gate FET, and the multi-gate FET formed, by providing a substrate, such as a silicon on insulator, silicon on sapphire, or bulk silicon wafer, having an active semiconductor layer, such as a layer of silicon, silicon germanium, silicide, or titanium silicide, is provided. A pad layer is provided over the substrate whereby the pad layer further has a plurality of etch stop layers. Preferably, the pad layer comprises a first pad layer and a second pad layer having a plurality of etch stop layers over the first pad layer. More preferably, the pad layer comprises first a pad oxide layer deposited by CVD to a thickness ranging from about 30 A to about 300 A, followed by a pad nitride layer comprising silicon nitride layers deposited by nitridization or CVD to a thickness ranging from about 800 A to about 10,000 A. The pad nitride layer further has the plurality of etch stop layers, preferably a plurality of oxide etch stop layers comprising silicon dioxide deposited to a thickness ranging from about 5 A to about 50 A during deposition of the pad nitride layers. The plurality of oxide etch stop layers deposited periodically therethrough the pad nitride layer adapt the substrate to be connected to a plurality of contacts having varying depths.
Alternatively, the first pad layer, or the pad oxide layer, may further have a plurality of etch stop layers preferably deposited periodically during deposition of the first pad layer, or pad oxide layer. Preferably in such alternate embodiment, the plurality of first pad layers comprise a plurality of pad oxide layers having a plurality of nitride etch stop layers deposited periodically during deposition of the pad oxide layer. More preferably, the pad oxide layer with the plurality of nitride etch stop layers is deposited to a combined thickness of about 2000 A with the plurality of nitride etch stop layers deposited to a thickness of about 10 A about every 200 A of the pad oxide layer deposition.
Subsequently, a vertical trench is formed whereby the vertical trench traverses through the first pad layer and second pad layer having the plurality of etch stop layers stopping at a surface of the active semiconductor layer of the substrate. A vertical channel is then formed in the vertical trench, preferably by growing the active semiconductor layer, and subsequently first and second vertical gates are formed within the vertical channel.
Preferably, the vertical trench is formed by first etching a top surface of the second pad layer stopping at a top surface of the first pad layer. A conformal layer is then provided over a surface of the substrate thereby at least coating the trench with the conformal layer. Preferably, the conformal layer is an insulating material comprising ASG, BPSG, PSG, or combinations thereof, deposited to a thickness ranging from about 200 A to about 2000 A. A filler material, comprising polysilicon, carbon, germanium oxide, germanium nitride, TiO2, or combinations thereof, is then provided over the substrate to at least filling remaining portions of the trench. First and second spacers are then formed by etching the conformal layer, therein also forming an isolation region which isolates the vertical double gate FET from adjacent FETs on a single die. The isolation is then filled with an isolation material, preferably silicon dioxide or BPSG, thereby separating the vertical double gate FET from adjacent FETs on a single die. An underlying portion of the active semiconductor layer is then exposed by etching the filler material and any underlying portions of the first pad layer.
In yet a further aspect, in an embodiment wherein the active semiconductor layer comprises a silicide disposed upon silicon, the step exposing an underlying portion of the active semiconductor layer is performed by etching the filler material, any underlying portions of the first pad layer, and over-etching the substrate down to an active silicon layer of the substrate wherein the active silicon layer acts as a seed layer for the subsequent epitaxial growth procedure.
Once the active semiconductor layer is exposed the vertical channels are then formed by epitaxially growing the exposed portion of the active semiconductor layer. First and second vertical gates may then be formed within the vertical channel. Preferably, the first and second vertical gates are formed by forming conductor holes by patterning and etching the first and second spacers to expose an underlying portion of the first pad layer. Thin diffusion regions are then formed in the conductor holes by growing the exposed first pad layer to at least fill a portion of the conductor holes. The conductor holes may then be provided with a gate material, preferably polysilicon, titanium, tungsten aluminum, or gold, to a thickness ranging from about 5 nm to about 100 nm whereby the gate material fills the remaining portions of the conductor holes to form the first and second gates.
A plurality of contacts having varying dimensions are provided for connection to the substrate. In connecting the plurality of contacts to the substrate, a plurality of openings are formed within the substrate wherein the openings are adapted to connect with selected ones of the plurality of contacts having varying dimensions. Preferably, a first opening of the plurality of openings traverses through the substrate connecting to the vertical channel, while a second opening traverses through the substrate connecting to the active region, while still other openings traverse through the pad layer stopping at a selected one of the plurality of etch stop layers.
In another aspect of the present invention, the first and second gates may be extended, preferably horizontally, by depositing additional gate material over the surface of the openings which traverse through the pad layer stopping at selected ones of the plurality of etch stop layers.
Subsequently, the plurality of contacts are connected to the substrate whereby at least one of the contacts connects to the vertical channel, at least one of the contacts connects to the second opening traversing through the pad and plurality of etch stop layers stopping at the active semiconductor layer of the substrate, while still other contacts of the plurality of contacts connect to the extended first and second gates. In the preferred embodiment, the substrate may also be provided with source and drain regions wherein the source and drain regions are provided at the first and second openings traversing through the pad and plurality of etch stop layers. Thus, the present invention provides a first vertical gate FET adapted to be connected to a single die wherein the die has on a surface thereof at least a second vertical gate FET having a differing gate length than a gate length of the first FET, the second FET being made by the above process. In yet a further embodiment, the present invention provides a method of making a die having multiple FETs with varying gate lengths by providing a die with a first FET having a first gate length whereby the FET is made by the steps of: a) providing a substrate having an active layer; b) providing a pad layer having a plurality of etch stop layers periodically therethrough over the substrate; c) providing a plurality of contacts having varying dimensions; d) forming a plurality of openings adapted to connect with the plurality of contacts having varying dimensions wherein at least first and second openings traverse through the pad and plurality of etch stop layers, while other openings traverse through the pad layer stopping at selected ones of the plurality of etch stop layers; e) forming a vertical channel in the first opening traversing through the pad layers and the plurality of etch stop layers; f) forming at least first and second vertical gates in the vertical channel; and g) connecting the plurality of contacts to the substrate whereby at least one of the contacts connects to the vertical channel, while at least another of the contacts connects to the second opening traversing through the pad and plurality of etch stop layers, while still other contacts connect to the first and second gates, thereby providing the first FET having a first gate length over the die. The die is then provided with a second FET made by repeating the above steps a) through g) to provide a plurality of FETs having differing gate lengths over a single die.